Abstract
Evolutionary techniques may be applied to search for specific structures or functions, as specified in the fitness function.
This paper addresses the challenge of finding an appropriate fitness function when searching for generic rather than specific
structures which, when combined wiacteristic of defect tolerance on the circuit. Production defects for integrated circuits
are expected to increase considerably. To avoid a corresponding drop in yield, improved defect tolerance solutions are needed.
In the case of Field Programmable Gate Arrays (FPGAs), the pre-designed gate array provides a bridge between production and
the application designers. Thus, introduction of defect tolerant techniques to the FPGA itself could provide a defect free
gate array to the application designer, despite production defects. The search for defect tolerance presented herein is directed
at finding defect tolerant structures for an important building block of FPGAs: Look-Up Tables (LUTs). Two key approaches
are presented: (1) applying evolved generic building blocks to a traditional LUT design and (2) evolving the LUT design directly.
The results highlight the fact that evolved generic defect tolerant structures can contribute to highly reliable circuit designs
at the expense of area usage. Further, they show that applying such a technique, rather than direct evolution, has benefits
with respect to evolvability of larger circuits, again at the expense of area usage.
This paper addresses the challenge of finding an appropriate fitness function when searching for generic rather than specific
structures which, when combined wiacteristic of defect tolerance on the circuit. Production defects for integrated circuits
are expected to increase considerably. To avoid a corresponding drop in yield, improved defect tolerance solutions are needed.
In the case of Field Programmable Gate Arrays (FPGAs), the pre-designed gate array provides a bridge between production and
the application designers. Thus, introduction of defect tolerant techniques to the FPGA itself could provide a defect free
gate array to the application designer, despite production defects. The search for defect tolerance presented herein is directed
at finding defect tolerant structures for an important building block of FPGAs: Look-Up Tables (LUTs). Two key approaches
are presented: (1) applying evolved generic building blocks to a traditional LUT design and (2) evolving the LUT design directly.
The results highlight the fact that evolved generic defect tolerant structures can contribute to highly reliable circuit designs
at the expense of area usage. Further, they show that applying such a technique, rather than direct evolution, has benefits
with respect to evolvability of larger circuits, again at the expense of area usage.
- Content Type Journal Article
- Pages 281-303
- DOI 10.1007/s10710-011-9129-2
- Authors
- Asbjoern Djupdal, CRAB Lab, IDI, NTNU, Trondheim, Norway
- Pauline C. Haddow, CRAB Lab, IDI, NTNU, Trondheim, Norway
- Journal Genetic Programming and Evolvable Machines
- Online ISSN 1573-7632
- Print ISSN 1389-2576
- Journal Volume Volume 12
- Journal Issue Volume 12, Number 3